Moving the part is one way to correct that problem, but you then need to check all the connections on the part to make sure they are all connected (in this case they weren’t which caused the problem). I expect the +5V connection to the neo pixel was not actually connected to the neo pixel in the original sketch. When you moved the neo pixel because +5V wasn’t connected that connection didn’t move with the neo pixel (because Fritzing didn’t know it should connect there) leaving the +5V connection unconnected with the wire hanging in space (and that in turn reflects in to breadboard and schematic view potentially causing problems there as well). Worse, if that dangling wire contacts a pin on the neo pixel (which it didn’t in this case) it will make a connection there where you don’t want one. If you put the cursor on the pin of a part (for example the +5V pin on the left of the top neo pixel) and left click the mouse button all connections will highlight in yellow. In the example the +5V wire on the neopixel, the T that denotes the +5V net and the +side of the capacitor all turn yellow indicating that these three points are connected together as they should be. After moving a part you should check all the pins to make sure that the connections all still go where they are supposed to. If you try the same thing on your Chewie original circuit.fzz you will see that the schematic looks (and is) incorrect, although it is not quite as incorrect as it first looks (likely a Fritzing bug here). If you left click on the ground pin the - terminal of the cap, the ground pin and the ground pin of the neopixel all light up yellow indicating a connection, even though on the screen the ground wire to the neopixel ends below the neopixel and does not appear to connect. Same with the di pin, while it appears on the screen to connect on or near neopixel ground, it really is on di. Selecting the neo pixel and moving it slightly causes the screen to update correctly showing the di and ground connections (with ugly wire layout) and the +5V neo pixel unconnected which is what pcb view is showing. I usually prefer to lock the parts in place and either move the wires til I get a correct connection or delete the wire and rerun it to get a connection. The click to highlight the connections to this net (which works in all views) is a very useful tool for insuring you have all the connections you expected to. It is how I find these errors when a sketch is doing something unexpected.
Ah! now it makes sense. Either method (mounted on the pcb or connected via wires to the pcb) should work as long as the pot selected will fit inside the neo pixel ring (I assume there is a hole in the center of the ring). Then which ever method is easier mechanically is what you should do. If the enclosure has a lid where your board and the mega under your board can connect with the neo pixels the jacks and the pot will all come out one plate that should work (although it depends on the position of the holes in the enclosure plate exactly matching position on the pcb which can be a pain to do, with wires to the board the enclosure holes are independent of the panel hole dimensions as wires will bend unlike neo pixels or jacks soldered to a pcb 
. I usually opt to use wires to make my life easier but either will work.
The issue with the power wiring to the neo pixels is voltage drop at high current. The neo pixels sometimes when many or all the leds are on and the clocks align (which will be only sometimes) draw a lot of current. That current in turn causes voltage drop in either the wires or the PCB traces (which are effectively wires on the board). A high current caused voltage drop in the ground wire can reduce the noise margin for a low level (which is only .7V) and cause intermittent (and thus very hard to find) problems in the logic circuits and the mega. One way to avoid that is to run the power and ground wires for the two neo pixels from the power supply directly to the neo pixes (and the 1000uf capacitor which wants to be as close to the neo pixels as possible. The power and ground for the logic then uses a different set of wires (or traces on the pcb) also connected to the power supply at only one place You do not want to have two paths to the same point in any circuit (although it is most important in the power traces) as this causes a ground loop if the current causes a different voltage drop on the two halfs of the path which it will if the resistance of the two paths is not identical. Its best to not have any loops in any trace.
The way I deal with this (when I remember too, too often I make one more change before doing a backup and end up losing work) is to keep copies of working sketches. A version control system such as git, while complex to learn makes this relatively easy. Alternately (and much easier if you remember to do it) is just save a copy of the sketch to a new file name (whose name will tell you what state the project was in when it was saved). To make changes copy that sketch in to a new .fzz file with a new name and make your changes. If you screw it up (which I do all to often)
you can go back to the saved file and try again. If you are successful with making some number of changes, again save that working sketch in a new file name (this is what I’m typically don’t do ) so you can go back to the saved copy when you screw up.
As well something I did but didn’t mention: in pcb view you should click on routing->Design Rules Check (DRC). This will check the clearances of all traces in the pcb (it finds a lot of problems in your current pcb!). For a board this simple the standard rules should do just fine, although the pot inside the neo pixel part will generate an error that can be ignored. It looks like some of your traces are too close to each other.
Peter