I'm not smart enough to know what I disturbed when I mod-ed the FET svg - I just push nodes about -, so I don't know what happened. I put copper0 in copper1 to the new std, and I was getting an error that FZ can't do separate copper layers.
I've mod-ed this PCB svg for the 3rd time and it seam ok now. I mod-ed the FET twice but now I mod-ed the V-reg.